(1) Field of the Invention
The present invention relates to the manufacture of semiconductor devices in general, and in particular, to a method of forming a dual damascene using a partial hard A mask open process, especially suited for low-k dielectric structures.
(2) Description of the Related Art
Dual damascene process xe2x80x94which is explained more in detail belowxe2x80x94 makes it possible to inlay within a surface a dual layered structure, such as a trench and a smaller hole vertically through it to make connection to a lower level structure, which then can be filled with a filler material. In the semiconductor industry, the filler material is usually a metal, and the dual damascene structure, a metal interconnect which comprises a metal line in the trench and the via or contact metal in the hole that makes connection to the next level of an integrated circuit. Forming the trench to a particular depth from the surface, and then forming the hole, in this or reverse order, requires precise process steps, including masks for patterning the various shapes and sizes of trenches, and the more uniformly shaped holes on and within the structure. Usually a single mask is used for a single layered damascene structure while dual masks are used for a dual damascene structure where each mask determines the depth at which each layer of the two level structure stops. For this reason, these masks are sometimes referred to as xe2x80x9cetch-stopxe2x80x9d layers, as is well known in the art. However, it is disclosed later in the embodiments of the present invention a method of forming dual damascene structures with a partial hard mask through a judicious use of partial opening or etching of the mask which simplifies the dual damascene process, and makes it especially suitable for low-k dielectric materials in advanced sub-micron technologies capable of forming features approaching less than 0.10 micrometers (xcexcm).
In one approach for a dual damascene process shown in FIG. 1a, two insulative layers (120) and (130), sometimes referred to as intermetal dielectrics (IMD), are formed on a substrate (100) with an intervening etch-stop or trench-stop layer (125). Substrate (100) is provided with metal layer (110) and another etch-stop layer or via-stop liner (115). Metal layer can be the commonly used aluminum or copper, while the liner can be another dielectric layer. A desired trench or trench pattern (150) is first etched into the upper insulative material (130) using conventional photolithographic methods and photoresist (140). The etching stops on trench-stop layer (125). Next, a second photoresist layer (160) is formed over the substrate, thus filling the trench opening (150), and patterned with hole opening (170), as shown in FIG. 1b. The hole pattern is then etched into the lower insulative layer (120) as shown in FIG. 1c and photoresist removed, thus forming the dual damascene structure shown in FIG. 1f.
Or, the order in which the trench and the hole are formed can be reversed. Thus, the upper insulative layer (130) is first etched, or patterned, with hole (170), as shown in FIG. 1d. The hole pattern is also formed into etch-stop layer (125). Then, the upper layer is etched to form trench (150) while at the same time the etching transfers the hole pattern in the etch-stop layer into lower insulation layer (120), as shown in FIG. 1e. It will be noted that trench-stop layer (125) stops the etching of the trench into the lower insulation layer. Similarly, via-stop layer (115) also stops etching. However, layer (115) at the bottom of opening (170) is removed before metal is deposited at the next step. Thus, after the completion of the thusly formed dual damascene structure, both the hole opening and trench opening are filled with metal (180), and any excess material on the surface of the substrate is removed by chemical mechanical polishing, as seen in FIG. 1f. 
In prior art, various methods of forming damascene structures are described. In U.S. Pat. No. 6,140,220, Lin discloses a method in which the via hole is first lined with a layer of silicon nitride prior to adding a diffusion barrier and copper. This allows use of a barrier layer that is thinner than normal so that more copper may be included in the via hole, resulting in an improved conductance of the via. Another method is disclosed in U.S. Pat. No. 6,077,769, by Huang, et al., in order to overcome the narrowing of a damascene hole, which causes increased contact resistance. They accomplish this by avoiding the use of a conventional etching process with a very high SiO2/SiN etching selectivity ratio. In still another U.S. Pat. No. 6,140,226, by Grill, et al., a different approach for forming dual damascene comprises a dual patterned hard mask which is used to form dual relief cavities with a first set of one or more layers with a first pattern, and a second set of one or more layers with a second pattern. On the other hand, Buramanian, et al., disclose in U.S. Pat. No. 6,127,089 a method of forming a dual damascene structure with low k dielectric materials by employing an imageable layer that is convertible to a hard mask upon exposure to a plasma etch that etches the low-k dielectric material.
It is disclosed later in the embodiments of the present invention a different method of forming a dual damascene structure with the use of a single hard mask that is partially opened initially to form a trench, and the via or contact hole at a later step.
It is therefore an object of this invention to provide a method of forming a dual damascene structure with the use of a partial hard mask open process.
It is another object of the present invention to provide a method of forming a dual damascene using fluorine-related etch chemistry in the hard mask open approach.
It is yet another object of the present invention to provide a method of forming a dual damascene having a porous low-k dielectric structure.
It is still another object of the present invention to provide a method of forming a dual damascene having a hybrid low-k dielectric structure.
It is an overall object of the present invention to provide a method of forming dual damascene structures especially suitable for advanced sub-micron technologies having features approaching less than 0.10 microns.
These objects are accomplished by providing a substrate having a via-stop layer formed over a first metal layer formed on a substrate; forming a dielectric layer over said via-stop layer; forming a hard mask over said dielectric layer; etching a partial trench opening in said hard mask; forming a via pattern photo mask over said substrate, including said partial trench opening; etching said via pattern in said photo mask into said partial trench opening in said hard mask; transferring said via pattern in said hard mask partially into said dielectric layer; extending said partial trench opening in said hard mask into the full depth of said hard mask; transferring said full depth trench in said hard mask into said dielectric layer; extending said via pattern partially in said dielectric layer into said via-stop layer until reaching said first metal layer; and forming second metal in said trench and via to complete said dual damascene process.